`timescale 1 ns / 1 ps

`define __SIM__

module tb; 

reg clk ; 

reg rst_n;          //复位信号

`define SYS_FREQ 50_000_000
//生成时钟
parameter NCLK = 1000/(`SYS_FREQ/1000000.0);  // 
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end

/*---------------------------- mcu nets --------------------------*/


/*----------------------------- 模块 ------------------------------*/
top u_top
(
    .clk(clk)
);

reg [31:0] dlt = 0 ;
reg [31:0] pwm;
always @(posedge clk) begin 
    if(u_top.wb_stb & u_top.wb_we & !u_top.wb_ack ) begin
        if(u_top.wb_adr == 32'h80000000)begin
            // $display("%d ns | dlt %d ns | Write @ 0x%08x: 0x%08x [led]",$time ,$time - dlt  ,u_top.wb_adr  ,u_top.wb_dat) ;
        end
        else if(u_top.wb_adr == 32'h80010000)begin
          //  $display("%d ns | dlt %d ns | Write @ 0x%08x: %032b [spi]",$time ,$time - dlt  ,u_top.wb_adr  ,u_top.wb_dat) ;
        end
        else if(u_top.wb_adr == 32'h80000300)begin
            $display("%d ns | dlt %d ns | Write @ 0x%08x: %032b [i2c]",$time ,$time - dlt  ,u_top.wb_adr  ,u_top.wb_dat) ;
        end
        else if(u_top.wb_adr == 32'h80000400)begin
            $display("%d ns | dlt %d ns | Write @ 0x%08x: %d [txd]",$time ,$time - dlt  ,u_top.wb_adr  ,u_top.wb_dat[0]) ;
        end
        else if(u_top.wb_adr == 32'h80000500)begin
            $display("%d ns | dlt %d ns | Write @ 0x%08x: 0x%08x [28byj-48]",$time ,$time - dlt  ,u_top.wb_adr  ,u_top.wb_dat) ;
        end
        else if(u_top.wb_adr == 32'h80000600)begin
            $display("%d ns | dlt %d ns | Write @ 0x%08x: 0x%08x [pwm]",$time ,$time - dlt  ,u_top.wb_adr  ,u_top.wb_dat) ;
            pwm <= u_top.wb_dat;
        end
        else if(u_top.wb_adr == 32'h8000ff00)begin
            $display("%d ns | dlt %d ns | Write @ 0x%08x: 0x%08x %d [debug]",$time ,$time - dlt  ,u_top.wb_adr  ,u_top.wb_dat ,u_top.wb_dat) ;
        end
        else begin
            // $display("%d ns | dlt %d ns | Write @ 0x%08x: 0x%08x ",$time ,$time - dlt  ,u_top.wb_adr  ,u_top.wb_dat) ;
        end
        dlt = $time;
    end 



    //读数据
    if(u_top.wb_stb & !u_top.wb_we & !u_top.wb_ack ) begin
        // if(u_top.wb_adr == 32'h80000300)begin
        //     $display("%d ns | dlt %d ns | Read  @ 0x%08x: [i2c] ",$time ,$time - dlt  ,u_top.wb_adr   ) ;
        // end else begin 
            // $display("%d ns | dlt %d ns | Read  @ 0x%08x: ",$time ,$time - dlt  ,u_top.wb_adr  ) ;
        // end 
    end
end 



initial begin
    $display(" -------- serv sim ----------");
    $display(" sys clock: %d MHz",1000/NCLK);
    rst_n = 0;
    repeat(20) @(posedge clk) ;
    rst_n = 1 ; 
    repeat(100000*1) @(posedge clk) ;
    $display("%d ns:done",$time);
	$dumpflush;
	$finish;
	$stop;	
end





endmodule
